This documentation is no longer maintained. For documentation of the current version of emc2, please see http://www.linuxcnc.org/docview/html

About pluto_servo

Pluto_servo is an emc2 software driver and associated firmware that allow the Pluto-P board to be used to control a servo-based CNC machine. The Pluto-P is an inexpensive ($60) FPGA board featuring the ACEX1K chip from Altera. Pluto_servo is released under the terms of the GNU General Public License version 2. The pluto_servo system is suitable for control of a 4-axis CNC mill with servo motors, a 3-axis mill with PWM spindle control, a lathe with spindle encoder, etc. The large number of inputs allows a full set of limit switches.

The board features:

This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

Requirements

Obtaining the source code

The source code (including the verilog source code and Quartus project files) is included with the emc2 source in the src/hal/drivers/ directory.

Compilation and installation

Pluto_servo is built by the normal emc2 build process.

Rebuilding the FPGA firmware

Like the HAL hardware driver, the FPGA firmware is licensed under the terms of the GNU General Public License. The src/hal/drivers/pluto_servo_firmware/ subdirectory contains the Verilog HDL source code plus additional files used by Quartus—which are "scripts used to control compilation"—for the FPGA firmware. Altera's Quartus II software is required to rebuild it. The gratis version of Quartus II runs only on Microsoft Windows, although there is apparently a paid version that runs on Linux. To rebuild the firmware from the .hdl and other source files, open pluto_servo.qpf and press CTRL-L. Then, in Linux, recompile emc2.

Pinout

IN1 GND ^^ Parallel port connector ^^ Power Jack >
IN2 VCC FPGA
IN3 IN4 OUT8 OUT9
IN5 IN6 OUT6 OUT7
IN7 GND OUT4 OUT5
LED OUT2 OUT3
IN0 UP0 UP1 GND DN3 UP3 QB0 VCC QZ0 QB1 QA2 QB2 OUT0 QB3 OUT1
DN0 GND DN1 DN2 UP2 GND QA0 VCC GND QA1 QZ1 GND QZ2 QA3 QZ3

The actual pinout used, using the FPGA pin numbering, is in src/hal/drivers/pluto_servo_firmware/pluto_servo.pin. (view CVS version).

Pinout Key

UPx
The "up" signal from PWM generator X (up/down mode) or "pwm" signal (pwm+dir mode). May be used as a digital output if the corresponding PWM channel is unused, or the output on the channel is always negative. Alternately, the corresponding digital output may be set to TRUE to make UPx active low rather than active high.
DNx
The "down" signal from PWM generator X (up/down mode) or "direction" signal (pwm+dir mode). May be used as a digital output if the corresponding PWM channel is unused, or the output on the channel is never negative. Alternately, the corresponding digital ouput may be set to TRUE to make DNx active low rather than active high.
QAx, QBx
The A and B signals for Quadrature counter X. May be used as a digital input if the corresponding quadrature channel is unused.
QZx
The Z (index) signal for quadrature counter X. May be used as a digital input if the index feature of the corresponding quadrature channel is unused.
INx
Dedicated digital input #x
OUTx
Dedicated digital output #x
GND
Ground
VCC
+3.3V regulated DC
Pin Alternate Functions
Primary functionAlternate function Behavior if both functions used
UP0 PWM0 When pwm-0-pwmdir is TRUE, this pin is the PWM output
OUT10 XOR'd with UP0 or PWM0
UP1 PWM1 When pwm-1-pwmdir is TRUE, this pin is the PWM output
OUT12 XOR'd with UP1 or PWM1
UP2 PWM2 When pwm-2-pwmdir is TRUE, this pin is the PWM output
OUT14 XOR'd with UP2 or PWM2
UP3 PWM3 When pwm-3-pwmdir is TRUE, this pin is the PWM output
OUT16 XOR'd with UP3 or PWM3
DN0 DIR0 When pwm-0-pwmdir is TRUE, this pin is the DIR output
OUT11 XOR'd with DN0 or UP0
DN1 DIR1 When pwm-1-pwmdir is TRUE, this pin is the DIR output
OUT13 XOR'd with DN1 or UP1
DN2 DIR2 When pwm-2-pwmdir is TRUE, this pin is the DIR output
OUT15 XOR'd with DN2 or UP2
DN3 DIR3 When pwm-3-pwmdir is TRUE, this pin is the DIR output
OUT17 XOR'd with DN3 or UP3
QZ0 IN8 Read same value
QZ1 IN9 Read same value
QZ2 IN10 Read same value
QZ3 IN11 Read same value
QA0 IN12 Read same value
QA1 IN13 Read same value
QA2 IN14 Read same value
QA3 IN15 Read same value
QB0 IN16 Read same value
QB1 IN17 Read same value
QB2 IN18 Read same value
QB3 IN19 Read same value

Notes:

Connectors

The Pluto-P board is shipped with the left connector presoldered, with the key in the indicated position. The other connectors are unpopulated. There does not seem to be a standard 12-pin IDC connector, but some of the pins of a 16P connector can hang off the board next to QA3/QZ3.

The bottom and right connectors are on the same .1" grid, but the left connector is not. If OUT2…OUT9 are not required, a single IDC connector can span the bottom connector and the bottom two rows of the right connector.

Pins

Read the ACEX1K datasheet for information about input and output voltage thresholds. The pins are all configured in "LVTTL/LVCMOS" mode and are generally compatible with 5V TTL logic.

Before configuration and after properly exiting emc2, all Pluto-P pins are tristated with weak pull-ups (20kΩ min, 50kΩ max). However, software bugs in the pluto_servo firmware or emc2, or a crash of the computer where emc2 is running, can leave the Pluto-P pins in an undefined state.

When the device is unprogrammed, the LED glows faintly. When the device is programmed, the LED glows according to the duty cycle of PWM0 (LED = UP0 xor DOWN0).

In pwm+dir mode, by default dir is HIGH for negative values and LOW for positive values. To select HIGH for positive values and LOW for negative values, set the corresponding dout-NN pin HIGH to invert the signal.

The index input is triggered on the rising edge. Initial testing has shown that the QZx inputs are particularly noise sensitive, due to being polled every 25ns. Digital filtering has been added to filter pulses shorter than 150ns (six polling times). Additional external filtering, such as a Schmitt buffer or inverter, RC filter, or differential receiver (if applicable) is recommended.

The IN1…IN7 pins have 22-ohm series resistors to their associated FPGA pins. No other pins have any sort of protection for out-of-spec voltages or currents. It is up to the integrator to add appropriate isolation and protection. Traditional parallel port optoisolator boards do not work with pluto_servo due to the bidirectional nature of the EPP protocol.

Power

A small amount of current may be drawn from VCC. The available current depends on the unregulated DC input to the board. Alternately, regulated +3.3VDC may be supplied to the FPGA through these VCC pins. The required current is not yet known, but is probably around 50mA plus I/O current.

The regulator on the Pluto-P board is a low dropout type. Supplying 5V at the power jack will allow the regulator to work properly.

PC interface

The "software EPP emulation" (epp_soft=1) is only partially implemented. An EPP-capable parallel port is currently a requirement.

At present, only a single pluto_servo board is supported. At present there is no provision for multiple boards on one parallel port (all boards reside at the same EPP address) but supporting one board per parallel port should be possible.

Input latching and output updating

PWM duty cycles for each channel are updated at different times.

digital outputs OUT0 through OUT9 are all updated at the same time. Digital outputs OUT10 through OUT17 are updated at the same time as the pwm function they are shared with.

Digital inputs IN0 through IN19 are all latched at the same time.

Quadrature positions for each channel are latched at different times.

For more information

A list of all HAL function names, pin names and parameter names is in the manual page, pluto_servo.9.

The Pluto-P board may be ordered from knjn.com (US based, international shipping is available). Some additional information about it is available from fpga4fun.com and from my blog.

A schematic for a 2A, 2-axis PWM servo amplifier board is available. The L298 H-bridge is inexpensive and can easily be used for motors up to 4A (one motor per L298) or up to 2A (two motors per L298) with the supply voltage up to 46V. However, the L298 does not have built-in current limiting, a problem for motors with high stall currents. For higher currents and voltages, some users have reported success with International Rectifier's integrated high-side/low-side drivers.

The details of the register set

The EPP protocol works by reading and writing values from registers on the connected device. However, the details of the register set are subject to change between releases of pluto_servo.